Components of a Processor 

Lesson 2

Recap

  1. Give a definition for the Fetch-Decode-Execute cycle.
     
  2. Name the 5 components of a processor. (Full names, not the abbreviations)
     
  3. Where are the contents of the MDR copied to in the cycle?
     
  4. In the context of the Fetch-Execute cycle, explain the significance of the Program Counter (PC) and the Current Instruction Register (CIR).

Recap

  1. The Fetch-Decode-Execute cycle is the cycle that the CPU follows from the moment a computer is turned on until it is shut down in order to process instructions that have been sent to it.
     
  2. Program Counter, Current Instruction Register, Memory Address Register, Memory Data Register, Accumulator
  3. The accumulator
     
  4. The Program Counter (PC) is the register that holds the address of the next instruction to be fetched.

    The Instruction Register (IR) is the register that holds the currently fetched instruction awaiting decoding

Lesson Objectives

To be able to:

  • Describe the factors affecting the performance of the CPU
     
  • Understand the use of pipelining in a processor to improve efficiency

Fetch-execute cycle

  • In the last lesson we looked at the fetch-execute cycle


     
  • How do machine code instructions relate to assembly language programs?

Address Buses

The width of an address bus determines the maximum possible memory addresses of the system. 

 

With an 8-bit address bus, the maximum number of memory addresses is 2^8 = 256. 

 

An average PC has a memory capacity of 4GiB (Gibi bytes), which is 2^32 bytes.

Therefore, it must have a 32-bit address bus. 

Data Buses

The data bus is bi-directional, as data can be sent both ways along the bus

The width of a data bus is defined by the number of wires or lines it contains.

 

If the data bus is the same width as a computer word, data can be transferred to and from memory in a single operation.

A computer word is how memory is split up into equal units, usually 8, 16, 32 or 64 bits. 

Format of instructions

Assembly language is very closely related to machine code

Generally, there is a one-to-one correspondence between a machine code instruction and its assembly language equivalent.

 

 

The architecture of a computer, including the word size and width of the address bus, determines the format of a machine code instruction. 

A machine code instruction

  • The basic structure of a machine code instruction is shown below, and then given in hexadecimal below that. 

C50D;                         load the contents of accumulator into location 0D

 

The equivalent assembly code instruction could be: 

LDA #13

The maximum size of the operand will depend on the width of the address bus. 

Factors affecting performance

  • The main factors that will affect processor performance are:
    • Clock speed
    • The number of cores in the processor 
    • The amount and type of cache memory

Factors affecting performance

  • The fetch-execute cycle is triggered by the clock pulses of the system clock.
    • The faster the clock speed is, the faster a computer can fetch, decode and execute instructions
      • This clock can change state many billions of times per second, recorded in GHz.
      • A 4GHz processor would tick 4 billion times per second.
    • A clock can be overclocked, which means it boosts the number of ticks per second, e.g., it would go from 2.5GHz up to 5GHz.

The system clock 

  • A series of regular ON/OFF signals are used to synchronise the operations of the processor components. 
    • Actions are usually carried out on the rising edge of the clock
    • Actions each take a fixed number of cycles to complete.

Number of Cores

  • Many computers today, including personal computers, have multiple cores
    • A dual-core computer has two processors linked together in the same integrated circuit
    • A quad-core computer will have four linked processors
      • When these work concurrently on different parts of the same task, it is called parallel processing​​​​​​​

 

  • Each core is theoretically able to process a different instruction at the same time with its own fetch-execute cycle, making a quad-core computer around 4 times faster than a single-core computer
    • However, the software may not always be able to take full advantage of all four processors

Cache memory

  • Cache is a small amount of super fast (but expensive) memory that stores data and instructions that have recently been used by the processor 
    • Level 2 cache is larger but not as fast as level 1 cache
    • Both types are help on the processor chip

Cache memory

  • Level 1 cache memory is split into instruction cache and data cache, so that data and instructions can be fetched simultaneously
     
  • The more cache memory a computer has, the more likely it is that it will not have to fetch the next instruction or data from RAM.
    • It will already have been loaded into the super fast cache memory from which it can be retrieved much quicker.

Pipelining

  • Pipelining is a technique used to improve the performance of a processor.
     
  • For example, by overlapping stages in the fetch-execute cycle, or by breaking down the stages in an arithmetic instruction
    • An instruction enters the pipeline and as soon as one stage has been completed, fetching , another instruction enters the pipeline
    • A third instruction can then enter before either of the others is complete
  • There may be 10 or 12 stages in the pipeline, with some stages taking longer than others