Cache prefetch in gem5
Introduction
As gem5, a software capable of a full-system simulation in computer architecture research, does not have a valid prefetch model for L2 cache in memory hierarchy, then that module needs to be developed in order to have better results, closer to real execution ones.
Agenda
- Introduction
- Mission statement
- List of features
- Development status
- Communication channels
- Documentation
Mission Statement
ARMv7 cache prefetch in gem5 is our attempt to have more accurate memory hierarchy results when making a full-system simulation. Our goal is to reduce the difference between real results in real hardware and simulations in gem5, so hardware designers could have the system tested before implementing.
Mission Statement
The general idea in the project is the following: system are usually tested using series of benchmarks to have information like power consuption, time of execution, instructions execution and price. Having a reliable simulation for certain system where we can run the same benchmarks as in real ones is a great resource. This project is about making gem5 behavior close enough to real hardware.
List of features
- Configurable features
- Prefetch depth
- Mode (miss only or always)
- Queue size
- Data flush
- Cache size up to 32 KB in L1
- Cache size up to 1 MB in L2
- Clock cycles delay = 1 in L1
- Clock cycles delay = 14 in L2
Development status
Up to now, we have been able to write a prefetcher for cache L1 and L2, and move from a 13% execution time mean error to a 11% execution time mean error compared to real hardware showing that memory hierarchy (the only thing changed) has improved accuracy.
Communication channels and Documentation
You are welcome to take a look at the project, download the code, commit changes, use it or just give feedback:
- Blog: http://ajgallegog.github.io/
- Wiki: https://github.com/ajgallegog/gem5_arm/wiki
- gem5 site: http://gem5.org/Main_Page