SPDY

A FASTER RISC PROCESSOR

DEVELOPERS



Alankrita Gautam
Anisha Grover
Rajat Srivastava
Samarth Saxena
Shashank Mehta
Yatin Tyagi

Under the able guidance of

DR. VASKAR RAYCHOUDHARY

AIM


To develop an ISA that
 
  1. Improves the speed of common cases 
  2. Remove unnecessary hardware  
  3. Reduce power consumption

DESIGN PRINCIPLES


Design Principle 1

Simplicity favors regularity

Design Principle 2

Smaller is faster

Design Principle 3

Make the common case fast

Design Principle 4

Good design demands good compromises.




Do one thing and do it better than anyone else

-- Jeff Hoffman   

Make 

the 

common 

case 

fast

INSTRUCTION SET ARCHITECTURE


KEY FEATURES

  • Variable size of opcode field
  • No. of Registers: 32
  • Length of Registers: 24 bits
  • Register Classification
    • Program Counter
    • 3 Loop Control Registers
    • 12 Saved Registers
    • 14 Temporary Registers

INSTRUCTION FORMATS



INSTRUCTION SIZE



SPDY has a reduced instruction size of 24 bits compared to MIPS 32 bits, thereby enabling lesser instruction memory consumption.


Further, because of the varying opcode field size,we succeeded in increasing the offset field size to 15 bits (in case of Branch Format) thereby increasing the memory reach to a greater extent, instead of original 15 bits

OPCODES



ARITHMETIC FORMAT



F: Format field
RS1: Source Register
RS2: Second Source Register
Rd: Destination Register
Opcode: Operation code

example: add $s1, $t1, $t3

BRANCH FORMAT


F: Format field
Offset: Offset to Address
Opcode: Operation code

example: br loop1

IMMEDIATE FORMAT


F: Format field
RS1: Source Register
Rd: Destination Register
Offset: Offset to Address
Opcode: Operation code

example: addi $s1, $s1, 4

Basic part is now done


So what is new in spdy?



DESIGN PRINCIPLE 3

Make the common case fast

LOOPING IN MIPS




HOW IMPORTANT IS LOOPING?


Looping is one of the most basic parts of any program.

Simple counters that go from 0 to, lets say, 10, are used in many programs.

In fact, many programs such loops are also nested.

So if these loops become faster, the program runs faster.  

LOOPING IN SPDY



LOOP CONTROL DATAPATH



COMPONENTS USED



The components used are :

Program counter, Instruction memory, Data memory, Control unit,Registers, ALUs, Multiplexers

CONTROL UNIT



CONTROL UNIT RTL




ALU



ALU RTL



REGISTER FILE



REGISTER FILE RTL


MEMORY

Memory Size of the SPDY microprocessor is 128 X 24 bits


LOOP CONTROL RTL





DATAPATH

DATAPATH



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