single issue
low power
risc processor
instruction set architecture
Our instruction length,
17 bits.
opcodes
WHy such opcodes ?
Function code removed.
We're accounting for all the instructions using the 5 bit opcode.
In addition, for the Memory instructions (GROUP-2), the last 2 bits of the opcode, are taken in as part of the constant (or offset).
This gives us the flexibility of having a constant (or offset) from 0 to 47, rather than 0 to 15.
it's low power consuming!
We use the gated clock, to reduce power consumption.
Basically, by this, clock isn't applied to FF when the circuit's idle.
Thus, FFs are prevented from changing values further.
Resulting in no switching of values in further combinational circuits.
And,
in CMOS Circuits, the maximum power loss comes form switching activity.
If the frequency of clock is high,
switching activity is high,
power consumed is also high!
An example of this implementation,
a (4 x 4) register file.
Sadly,
this low-power consumption feature comes with a few compromises.
-
gated clock leads to small delay.
- takes up more area & complicates the design.
now, the instruction formats
group-1
add sub and or mult
op : opcode
rs,rt : source registers
rd : destination register
example : add $d, $t, $s #$d=$s + $t
sll srl slt
op : opcode
rs,rt : source registers
c : constant
example : sll const, $t, $s # $t=$s << const
group-2
addi andi ori slti
op : opcode
rs,rt : source registers
c : constant
example : addi const, $t, $s # $t=$s + const
lw sw bne beq
op : opcode
rs,rt : source registers
off : offset
example : beq off, $t, $s #if(($t)==($s)) goto PC + off.
group-3
j
jr
components
The components used are :
Program counter, Instruction memory, Data memory, Control unit,Registers, ALUs, Multiplexers
The ALU
ALU (RTL schematic)
The control unit
control unit (rtl schematic)
register file
register file (rtl schematic)
instruction memory (rtl schematic)
Datapaths
The complete datapath
add, sub and other arithmetic operations.
lw sw
sll slr
