cy_rslt_t rslt;
    bool      write_val = true;
 
    // Initialize pin P0_0 GPIO as an output with strong drive mode and initial value = false (low)
    rslt = cyhal_gpio_init(P0_0, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG, false);
 
    // Write the value to the output pin
    cyhal_gpio_write(P0_0, write_val);

#include "cyhal_gpio.h"

int main(void)
{
    // เลือกขา GPIO ที่ต้องการใช้งาน
    cyhal_gpio_t gpioPin = CYHAL_GPIO_P15;

    // กำหนดขา GPIO เป็นเอาต์พุต (output)
    cyhal_gpio_init(gpioPin, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG, CYHAL_GPIO_DRIVE_HIGH);

    while (1)
    {
        // ทำการสลับค่าเอาต์พุตของขา GPIO
        cyhal_gpio_toggle(gpioPin);

        // อ่านค่าเข้าของขา GPIO
        bool readValue = cyhal_gpio_read(gpioPin);

        // ตรวจสอบค่าที่ได้จากการอ่านและทำการประมวลผลต่อไป
        if (readValue)
        {
            printf("GPIO Pin is HIGH\n");
        }
        else
        {
            printf("GPIO Pin is LOW\n");
        }
    }

    return 0;
}

cyhal_pwm_start and cyhal_pwm_stop functions can be used after PWM initialization to start and stop the PWM output.
    cyhal_pwm_t pwm_obj;
 
    // Initialize PWM on the supplied pin and assign a new clock
    rslt = cyhal_pwm_init(&pwm_obj, P0_0, NULL);
    CY_ASSERT(CY_RSLT_SUCCESS == rslt);
 
    // Set a duty cycle of 50% and frequency of 1Hz
    rslt = cyhal_pwm_set_duty_cycle(&pwm_obj, 50, 1);
 
    while (loop)
    {
        // Stop the PWM output
        rslt = cyhal_pwm_stop(&pwm_obj);
 
        // Delay for observing the output
        cyhal_system_delay_ms(5000);
 
        // (Re-)start the PWM output
        rslt = cyhal_pwm_start(&pwm_obj);
 
        // Delay for observing the output
        cyhal_system_delay_ms(5000);
    }

cyhal_pwm_start and cyhal_pwm_stop functions can be used after PWM initialization to start and stop the PWM output.
    cyhal_pwm_t pwm_obj;
 
    // Initialize PWM on the supplied pin and assign a new clock
    rslt = cyhal_pwm_init(&pwm_obj, P0_0, NULL);
    CY_ASSERT(CY_RSLT_SUCCESS == rslt);
 
    // Set a duty cycle of 50% and frequency of 1Hz
    rslt = cyhal_pwm_set_duty_cycle(&pwm_obj, 50, 1);
 
    while (loop)
    {
        // Stop the PWM output
        rslt = cyhal_pwm_stop(&pwm_obj);
 
        // Delay for observing the output
        cyhal_system_delay_ms(5000);
 
        // (Re-)start the PWM output
        rslt = cyhal_pwm_start(&pwm_obj);
 
        // Delay for observing the output
        cyhal_system_delay_ms(5000);
    }

#include "cy_pdl.h"
#include "cyhal.h"
#include "cybsp.h"
#include "cy_retarget_io.h"


int main(void)
{
    cy_rslt_t result;
    cyhal_adc_t adc_obj;
    cyhal_adc_channel_t adc_chan_0_obj;

    /* Initialize the device and board peripherals /
    result = cybsp_init() ;
    if (result != CY_RSLT_SUCCESS)
    {
        CY_ASSERT(0);
    }

    __enable_irq();

    / Initialize retarget-io to use the debug UART port /
    result = cy_retarget_io_init(CYBSP_DEBUG_UART_TX, CYBSP_DEBUG_UART_RX, CY_RETARGET_IO_BAUDRATE);
    CY_ASSERT(result == CY_RSLT_SUCCESS);

    / ADC conversion result. /
    int adc_out;

    / Initialize ADC. The ADC block which can connect to pin 10[6] is selected /
    result = cyhal_adc_init(&adc_obj, P10_6, NULL);

    // ADC configuration structure
    const cyhal_adc_config_t ADCconfig ={
        .continuous_scanning = false,
        .resolution = 12,
        .average_count = 1,
        .average_mode_flags = 0,
        .ext_vref_mv = 0,
        .vneg = CYHAL_ADC_VNEG_VREF,
        .vref = CYHAL_ADC_REF_VDDA,
        .ext_vref = NC,
        .is_bypassed = false,
        .bypass_pin = NC
    };

    // Configure to use VDD as Vref
    result = cyhal_adc_configure(&adc_obj, &ADCconfig);

    / Initialize ADC channel, allocate channel number 0 to pin 10[6] as this is the first channel initialized /
    const cyhal_adc_channel_config_t channel_config = { .enable_averaging = false, .min_acquisition_ns = 220, .enabled = true };
    result = cyhal_adc_channel_init_diff(&adc_chan_0_obj, &adc_obj, P10_6, CYHAL_ADC_VNEG, &channel_config);

    for (;;)
    {
        / Read the ADC conversion result for corresponding ADC channel. Repeat as necessary. */
        adc_out = cyhal_adc_read_uv(&adc_chan_0_obj);
        printf("ADC = %d\r\n", adc_out);
        cyhal_system_delay_ms(100);
    }
}

#include "cy_pdl.h"
#include "cyhal.h"
#include "cybsp.h"
#include "cy_retarget_io.h"


int main(void)
{
    cy_rslt_t result;
    cyhal_adc_t adc_obj;
    cyhal_adc_channel_t adc_chan_0_obj;

    /* Initialize the device and board peripherals /
    result = cybsp_init() ;
    if (result != CY_RSLT_SUCCESS)
    {
        CY_ASSERT(0);
    }

    __enable_irq();

    / Initialize retarget-io to use the debug UART port /
    result = cy_retarget_io_init(CYBSP_DEBUG_UART_TX, CYBSP_DEBUG_UART_RX, CY_RETARGET_IO_BAUDRATE);
    CY_ASSERT(result == CY_RSLT_SUCCESS);

    / ADC conversion result. /
    int adc_out;

    / Initialize ADC. The ADC block which can connect to pin 10[6] is selected /
    result = cyhal_adc_init(&adc_obj, P10_6, NULL);

    // ADC configuration structure
    const cyhal_adc_config_t ADCconfig ={
        .continuous_scanning = false,
        .resolution = 12,
        .average_count = 1,
        .average_mode_flags = 0,
        .ext_vref_mv = 0,
        .vneg = CYHAL_ADC_VNEG_VREF,
        .vref = CYHAL_ADC_REF_VDDA,
        .ext_vref = NC,
        .is_bypassed = false,
        .bypass_pin = NC
    };
    result = cyhal_adc_configure(&adc_obj, &ADCconfig);

    / Initialize ADC channel, allocate channel number 0 to pin 10[6] as this is the first channel initialized /
    const cyhal_adc_channel_config_t channel_config = { .enable_averaging = false, .min_acquisition_ns = 220, .enabled = true };
    result = cyhal_adc_channel_init_diff(&adc_chan_0_obj, &adc_obj, P10_6, CYHAL_ADC_VNEG, &channel_config);

    for (;;)
    {
        / Read the ADC conversion result for corresponding ADC channel. Repeat as necessary. */
        adc_out = cyhal_adc_read_uv(&adc_chan_0_obj);
        printf("ADC = %d\r\n", adc_out);
        cyhal_system_delay_ms(100);
    }
}

#include "cy_pdl.h"
#include "cyhal.h"
#include "cybsp.h"
#include "cy_retarget_io.h"


int main(void)
{
    cy_rslt_t result;
    cyhal_adc_t adc_obj;
    cyhal_adc_channel_t adc_chan_0_obj;

    /* Initialize the device and board peripherals /
    result = cybsp_init() ;
    if (result != CY_RSLT_SUCCESS)
    {
        CY_ASSERT(0);
    }

    __enable_irq();

    / Initialize retarget-io to use the debug UART port /
    result = cy_retarget_io_init(CYBSP_DEBUG_UART_TX, CYBSP_DEBUG_UART_RX, CY_RETARGET_IO_BAUDRATE);
    CY_ASSERT(result == CY_RSLT_SUCCESS);

    / ADC conversion result. /
    int adc_out;

    / Initialize ADC. The ADC block which can connect to pin 10[6] is selected /
    result = cyhal_adc_init(&adc_obj, P10_6, NULL);

    // ADC configuration structure
    const cyhal_adc_config_t ADCconfig ={
        .continuous_scanning = false,
        .resolution = 12,
        .average_count = 1,
        .average_mode_flags = 0,
        .ext_vref_mv = 0,
        .vneg = CYHAL_ADC_VNEG_VREF,
        .vref = CYHAL_ADC_REF_VDDA,
        .ext_vref = NC,
        .is_bypassed = false,
        .bypass_pin = NC
    };

    // Configure to use VDD as Vref
    result = cyhal_adc_configure(&adc_obj, &ADCconfig);

    / Initialize ADC channel, allocate channel number 0 to pin 10[6] as this is the first channel initialized /
    const cyhal_adc_channel_config_t channel_config = { .enable_averaging = false, .min_acquisition_ns = 220, .enabled = true };
    result = cyhal_adc_channel_init_diff(&adc_chan_0_obj, &adc_obj, P10_6, CYHAL_ADC_VNEG, &channel_config);

    for (;;)
    {
        / Read the ADC conversion result for corresponding ADC channel. Repeat as necessary. */
        adc_out = cyhal_adc_read_uv(&adc_chan_0_obj);
        printf("ADC = %d\r\n", adc_out);
        cyhal_system_delay_ms(100);
    }
}