Fetch Execute Decode II
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- Explain the relationship between the width of the address bus and the number of memory locations that can be addressed.
- Calculate the number of addressable memory locations provided by an address bus of a specified width.
Recap
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Instructions and data are stored in memory.
Instructions are fetched one at a time into the processor.
The instructions are decoded by the control unit.
The instructions are executed, sometimes using the arithmetic logic unit.
The Central Processing Unit (CPU) contains the Arithmetic/Logic Unit (ALU), Control Unit (CU) and registers.
Clock speed determines processor performance, i.e. the number of instructions per second.
Pipelining improves performance by overlapping parts of the fetch-decode-execute (F-D-E) cycle for multiple instructions.
Instructions and data
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In a computer everything is represented in binary.
This includes the instructions that the CPU needs to carry out.
Instructions and data are stored in RAM until they are needed by the CPU.
Each instruction and item of data is stored in a location in memory.
Each element of the memory has a unique address.
This means that each instruction has an address. The first memory element that contains the instruction is the address of that instruction.
Buses
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The CPU is connected to other components using a physical connection called a bus.
They are known as buses as they carry a number of bits of data simultaneously, in the same way that a bus carries many people at once.
There are three types of bus that connect to the components of the CPU and which connect the CPU to the rest of the computer’s components.
| Data bus |
Carries binary data from component to component – for example an instruction from RAM that is being transferred to the CPU. |
| Control bus |
Carries signals that control the CPU components – for example a signal to start fetching the next instruction. |
| Address bus |
Carries the address of a memory location – for example the address of an instruction being fetched from memory. |
Directionality of buses
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In the simple model of the computer discussed in these lessons, each of the three buses has directionality.
The control bus is bidirectional – it needs to carry status information to devices and to carry the status information signals that devices send back.
The data bus is bidirectional – two-way data transfer is required when reading and writing data to memory.
The address bus is unidirectional – the CPU can point to addresses in memory or to other devices, however those hardware components cannot point to an address in the CPU.
You will see this directionality represented in diagrams as single-ended or double-ended arrows.
Address bus
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Do you know the difference between a 32-bit and a 64-bit CPU?
32-bit processors are cheaper, but can only use a limited amount of RAM.
The ‘bandwidth’ of these CPUs relates to the size of the address bus.
It refers to the number of unique memory addresses that can be accessed.
Let’s look at this in more detail, using the example of a simplified CPU with a low bandwidth.
Address bus
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Consider a CPU with a 4-bit bandwidth (address bus). How many unique memory addresses can it access?
4-bit addresses range from 0000 to 1111 inclusive.
1111 in denary is 15 (plus 1 because we must include 0), which gives 16 addresses.
16 addresses is 24.
Remember the formula to find the number of patterns in any number of bits: 2n
This formula works for finding the maximum number of memory addresses as well.
Primary storage (memory)
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A 32-bit CPU can access 4,294,967,296 unique memory locations.
Each memory location consists of a row of cells. Let's consider a situation where the row is 8 cells long.
Each of the 4,294,967,296 different addresses points to a row of 8 bits (1 byte).
That’s why a 32-bit CPU can only use 4GiB of RAM.
4 GiB addresses x 1 byte wide
This formula works for finding the maximum number of memory addresses as well.
Memory (RAM)
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Random Access Memory (RAM) is volatile memory – this means that its contents are erased when its power supply is turned off.
RAM is often referred to as ‘primary storage’, as it sits close to the CPU.
However, it isn’t possible to keep a computer on permanently. So it is necessary to have somewhere to store the programs and data (that make a computer general purpose) when the power is switched off.
The non-volatile storage required for this job is most often a hard disk.
Hard disks are often referred to as ‘secondary storage’, to make them distinct from ‘primary storage’.
Review
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Explain the relationship between the width of the address bus and the number of memory locations that can be addressed.
- Each unique address identifies 1 row of memory cells.
- The more ‘bandwidth’ that is available in the address bus, the higher the number of individual addresses that can be accessed.
Calculate the number of addressable memory locations provided by an address bus of a specified width.
- Use 2n to calculate the number of addresses that can be accessed by the CPU.
Fetch Execute Decode II P03c Explain the relationship between the width of the address bus and the number of memory locations that can be addressed. Calculate the number of addressable memory locations provided by an address bus of a specified width.
p03c Fetch Execute Decode II
By David James
p03c Fetch Execute Decode II
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