Smart Queue Monitoring System
Project Details-Video
Abstract: A smart queuing system is a system that can guide people (in a retail or public transportation setting) towards queues with the least waiting time to reduce congestion.
Project Structure
Task 1: Proposal Submission
Course Objective: Broader course objective for choosing the right hardware
- Proposal Retail Sector: Link
- Real-World Scenarios: Most of them will not come from a hardware/electronics background
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The proposal indicates the important requirements of each sector. It consists of the following:
1- Power Requirements
2- Space Requirements
3- Economic Constraints
4- Queue Parameters
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Solution Retail Sector: Link
Task-1-Completion Checklist
Project Build and Setup
Project Setup
- Video file for each sector is provided to them, they have to directly use it in the model file
- Model- You can use the person-detection-retail-0013 model for identifying the people
- Link to Model file- for starter-here
- Queue Parameters
- Coordinates of the Video given to them
- And they have to use the parameters from their proposals from task1
- Model Solution file-here
Course Objective: The student will be able to use the OpenVino toolkit to download the model files
Task-2
Deployment of the Model- Task3
- Course Objective: The student will be able to segregate their workload onto different hardware accelerators.
- The students will be able to run correct precision models on different hardware sets
- The student will be able to decide on the merits and demerits of each hardware and choose the right hardware for their application.
- Use of DevCloud for deployment on
- CPU
- GPU
- For Deployment on VPU
- Intel NCS2 stick used
- But what will the students do?
- FPGA Deployment not done since
- Versioning problem present on the Devcloud
- Do not have access to actual FPGA hardware
- Demo
Deployment of the Model- Task3
Demo- Retail Sector
Checklist for Task 3
Demos for other sectors- Manufacturing- FPGA
Demos for other sectors- Transportation
ReadMe File- Walkthrough- Link
FPGA Issues
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By archana iyer
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