Nearly Optimal Register Allocation using PBQP

New register Allocator

for

Nvidia Compiler

• Modelling Irregular Architecture

  • ​FP 16, 32, 64 and vector registers

• Improving Runtime Performance

Terminologies

• Virtual Register
• Mapping Vreg to
  • Physical Register 
  • Spill
• Cost Vector
• Cost Matrix
• FP 16, 32, 64
• Vector
• Interference graph

1) INITIALIZE VIRTUAL REGISTERS

• Data Structure

  • Array

• initialize Cost Vector

• How does Constraints affects Cost vector?

2) Populate Cost Matrix  

• For each edge in graph
• uses Cost vectors of Source and Destination
• What is Global Cost Matrix ?
  • Why to use ?
• Data Structure
  • 2D array for storing Cost matrix for each edge
  • GCM for fast Retrieval.

3) Reduce Graph

• What is reduce graph ?

  • reduce1, reduce2, reduceN

• Data Structure

  • Singly Linked List for each Degree

  • Why to go for Separate Lists ?

• Populate virtual registers in appropriate Degree List

• Add Vector Constraints

• While No DegreeList in Empty

  • Perform reduce1()

  • Perform reduce2()

  • Perform reduceN()

• Propagate Solution